Phase locked loops (PLLs) are commonly used in integrated circuit chips and systems to generate a signal that has a frequency and phase related to an input signal, called a reference signal. The reference signal is typically a clock signal. The output signal of the PLL is typically also a clock signal that is “locked” to the input reference clock signal. PLLs are used in a wide variety of chips including microprocessor, communications, and other electronics.
A typical PLL includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF) (which may be a low-pass filter), a voltage controlled oscillator (VCO), and frequency divider circuit. The PFD compares the phase of the reference signal with a feedback signal from the frequency divider circuit. Depending on the relationship of the phase of the reference signal and the feedback signal, the PFD provides a signal(s) to the CP that instructs the CP to increase or decrease the voltage to the VCO through the LF. The LF may integrate the signal to smooth it. The smoothed signal is provided to the VCO. The frequency of the VCO increases or decreases depending on the voltage signal from the LF. The output of the VCO is fed back to the PFD through the frequency divider in a loop that causes the output signal of the VCO to have a frequency that is proportional to (or equal to) and in phase with the reference signal.
Many PFDs can respond to frequency differences, which increases the lock-in range of allowable inputs. Some PLLs include a divider circuit between a reference clock signal and the reference input to the phase detector. In some designs, there are two outputs of the PFD: one with an up signal that causes the CP to increase the voltage to the VCO and another with a down signal that causes the CP to decrease the voltage to the VCO.
Adaptive-bandwidth PLL refers to a class of PLL that scales its dynamics proportionally with the operating frequency largely regardless of the process, voltage, and temperature (PVT) variations.
One of the challenges that analog PLL designers face today is the reduction in the ring VCO frequency range. The usable range of the VCO control voltage has shrunk considerably as the supply voltage has scaled below 1.2V (volts). On the other hand, the PLL application space continues to expand, demanding even wider frequency range from a single PLL.